(1) Field of the Invention
The invention relates to the field of silicon integrated circuits that include capacitor arrays, particularly for use in analog-to-digital and digital-to-analog converter circuits.
(2) Description of the Prior Art
Analog-to-digital converters operate on the general principle of successively dividing an analog voltage by 2 and then determining whether or not there is a remainder (by comparing the quotient with a preset standard value). In conventional (macro) circuitry, the voltage division is accomplished by applying the full voltage across two resistors of identical value that have been connected in series and then reading the value across one of them. While voltage dividers of this s are conceptually quite straightforward, they require resistors of great precision (generally better than 1%). This is not difficult to achieve in macrocircuits since the resistors can be individually trimmed to very close tolerances.
It turns out that in microcircuits based on Field Effect Transistor (FET) technology, it is easier to manufacture matching capacitors as opposed to matching resistors in the right resistance range. When voltage is applied across two capacitors in series, charge, rather than voltage, is shared between them, but the net effect is the same in terms of application to analog-to-digital converters. Similar considerations also point to the usefulness of precision capacitor arrays in digital-to-analog converters.
Capacitor arrays for the applications being discussed herein often share a common, grounded, base electrode and a common layer of capacitor dielectric material. Differentiation into the individual capacitors that comprise the array is then achieved by etching the second (upper) conducting layer into individual, electrically separate, upper electrodes.
The formation of these individual electrodes is achieved through standard photolithographic processes--photoresist masking followed by etching. While the state of the art permits very precise control of the dimensions of the photoresist mask, subsequent etching of the upper conducting layer does not always proceed uniformly over the entire surface. In particular, we have observed that the upper electrodes that lie on the periphery of the array tend to end up slightly smaller than the electrodes in the body of the array.
McNutt et al. (U.S. Pat. No. 5,322,438 Jun. 1994) discuss a variety of layout criteria that pertain to capacitor arrays and their optimization within silicon integrated circuits. One of their criteria involves the placement of grounded dummy unit capacitors around the periphery of each capacitor array. These units are identical in size and shape to the capacitors in the array but do not share either the lower conductive layer or the dielectric layer with the array. The dummy units, in addition to being grounded, are electrically connected to the array capacitors.